1. Field of the Invention
The present invention relates to a phase-locked loop device and more particularly to a phase-locked loop device with switched-delay phase frequency detector.
2. Description of the Related Art
A phase-locked loop (PLL) device, is a major component applied in frequency generators, wireless receivers, communication devices and so on. Referring to FIG. 1. FIG. 1 is a schematic diagram of a conventional PLL device. PFD unit 11 receives a reference clock signal REF_CK and a feedback clock signal FBK_CK and measures the phase and frequency difference therebetween to output phase difference signals, UP and DN. Charge pump circuit 12 receives and transforms the phase difference signals UP and DN into a current to charge loop filter 13. In FIG. 1, a circuit of a conventional loop filter 13 is provided. The loop filter 13 receives the current from charge pump circuit to limit the rate of change of a capacitor voltage, VCON, resulting in slow rising or falling voltage corresponding to the phase and frequency differences. The voltage-controlled oscillator (VCO) 14 generates an output clock signal according to the voltage VCON. Feedback divider 15 has a parameter N to generate the feedback clock signal FBK_CK, wherein the period of the feedback clock signal FBK_CK is N times the period of the output clock signal. In an ideal situation, when the PLL is in in-lock state, the phase difference signal UP synchronizes to the phase difference signal DN.
FIG. 2 is a schematic diagram of a phase frequency detector and charge pump circuit. The phase frequency detector 21 comprises a first D flip-flop 23, a second D flip-flop 24, an AND gate 26 and a delay unit 25 with a delay Td. The phase frequency detector 21 output two signals UP and DN to control the charge pump circuit 22. When the phase frequency detector 21 and the charge pump circuit is locked in a PLL device, the timing diagram of a related signal of the phase frequency detector 21 is shown in FIG. 3, where the high-level pulse widths of signals UP or DN respectively are Tpup and Tpdn. Assume the signals UP and DN are perfectly matched, in other words, Iup=Idn=I and Tpup=Tpdn=Td. When a PLL device is locked, the voltage on the loop filter is fixed because the net charge provided by the charge pump circuit should be zero. To maintain the locked condition, the following equation is satisfied:Iup·Tpup=Idn·Tpdn  (1)
However, if the current Iup and Idn are not matched, to satisfy the equation (1), the pulse widths Tpup and Tpdn need to be adjusted. Assume that the down current Idn is only 80% of the up current Iup, i.e. Idn=0.8·Iup. To satisfy the equation (1), the pulse width Tpdn is 125% of the pulse width Tpup. Because the phase frequency detector 21 aligns the falling edges of the signals UP and DN, the rising edge of the signal DN leads the rising edge of the signal UP due to the different pulse widths Tpup and Tpdn. If the duration of the pulse width Tpup is 1 ns, it results in a static phase error of 0.25 ns. Similarly, if the down current Idn is smaller than the up current Iup, the rising edge of the signal UP therefore leads the rising edge of the signal DN due to the different pulse widths Tpup and Tpdn.